Not Applicable.
Not Applicable.
The present invention relates to digital signal processors (DSPs) and more particularly to a bridge for connecting a digital signal processor (DSP) to an on-chip bus (OCB) such as an Advanced Microcontroller Bus Architecture (xe2x80x9cAMBAxe2x80x9d) Advanced High-performance Bus (xe2x80x9cAHBxe2x80x9d) as a slave.
The device known as the Digital Signal Processor, DSP, is a specialized microprocessor which can process signal streams with complex mathematical formulas in real time. A DSP is typically ten to fifty times more powerful than typical microprocessor devices such as the microprocessor cores used in application specific integrated circuits (ASICs). Applicant""s ZSP DSP has an open architecture which allows it to be easily programmed and used for numerous applications.
As complex cores, such as DSPs, are integrated in current and future generation ASICs, leading semiconductor companies are increasingly adopting standardized integration over On-Chip Busses (OCBs). OCB standardization facilitates a host of system on chip issues, including core portability, design reuse, leveraging common peripherals and processors, improving automated verification, and increasing customer capabilities to create products from a common design platform. Many widely used RISC (reduced instruction set computer) and DSP cores have their own complex and unique bus structures that often lack native provisions for straightforward integration with each other and supporting logic. A key need for multi-core systems is for buses to connect together these building blocks in a consistent manner that allows multiple cores to master the bus, rapidly moving large blocks of data and high-speed data transfer. These requirements drive the adoption of OCB standards.
Some additional business drivers for the adoption of OCB standards by semiconductor companies are: facilitating use of high value proprietary cores; reducing barriers to integrating proprietary cores from third party industry sources; providing a freely licensed and non-proprietary system framework and bus structure; reducing risk and engineering effort in system or ASIC integration and communication; minimizing interconnection issues to system companies; and, meeting industry standards for semiconductor vendor independence.
In order to support technical and business OCB requirements, a range of semiconductor companies are adopting the Advanced Microcontroller Bus Architecture (AMBA) for high performance proprietary core integration. AMBA was developed by ARM Inc. in collaboration with its semiconductor partners and put in the public domain to provide a de facto standard for integrating RISC processors to other proprietary cores and peripherals. The Open AMBA standard for a set of system busses for integrating processor and other proprietary cores defines the most widely implemented on-chip bus (OCB) in the industry. The AMBA standard version 2.0 defines three sets of busses, AHB (AMBA High-performance Bus), ASB (AMBA System Bus), and APB (AMBA Peripheral Bus). AHB was developed for on-chip bussing in high bandwidth processor cores.
The AMBA AHB is intended to address the requirements of high-performance synthesizable designs. It is a high-performance system bus that supports multiple bussed cores and provides high-bandwidth operation. The AHB is a single-edge timed, multiplexed data bus controlled by arbitration logic. AHB bus arbitration connects multiple processor and peripheral cores. AHB control signals define arbitration and decoding control of the bus and its interfaces. The AHB controls are not specific to a processor, but are optimized for memory systems. AHB supports block transfers and wider bus controls needed in high-speed high bandwidth systems.
As the applications have become more complex, e.g. multimedia wireless and broadband applications, DSPs have been increasingly used with ASICs to provide the required functionality. However, DSPs generally operate at clock frequencies higher than can be supported by the AMBA AHB and generally use different signal protocols. To realize the benefits of both ASICs and DSP, it would be useful to provide a means for coupling signals, including data and instructions, between the ASIC""s on-chip bus, such as the AMBA AHB, and a DSP despite the differing clock frequencies and signal protocols.
A DSP has internal memories to which it is tightly coupled to allow fast transfers of instructions and data between these memories and the DSP core. When a DSP is used with an ASIC, it may be desirable for masters in the ASIC to have access to the DSP internal memories. For example, a master in the ASIC could load the DSP memories before the DSP comes out of reset. An external, AHB based, DMA (direct memory access) controller may need direct access to the internal memories so that it can transfer data.
In accordance with the present invention, a bridge is provided between a direct memory access interface of a DSP and an ASIC on-chip bus which allows the DSP memory to operate as a slave on the on-chip bus. The bridge includes a slave engine which receives read and write requests from the on-chip bus and controls transactions with the DSP internal memories. The engine includes a request queue for storing and managing the read and write requests. It also includes a data buffer for temporary storage of data in read operations. A generic slave couples signals from the engine to the on-chip bus, providing compliance with the on-chip bus protocol. A pulse grower is used to couple signals from the engine to the generic slave and a pulse shaver is used to couple signals from the generic slave to the engine. The grower and shaver correct for the normally faster clock frequency of the DSP and engine as compared to the on-chip bus.